A new voting based hardware data prefetch scheme

The dramatic increase in the processor-memory gap in recent years has led to the development of techniques like data prefetching that hide the latency of cache misses. Two such hardware techniques are the stream buuer and the stride predictor. They have dissimilar architectures, are eeective for diierent kinds of memory access patterns and require diierent amounts of extra memory bandwidth. We compare the performance of these two techniques and propose a scheme that uniies them 1. Simulation studies on six benchmark programs connrm that the combined scheme is more eeective in reducing the average memory access time (AMAT) than either of the two individually.